Hardware Security & FPGA Engineering
Capabilities
RTL design in VHDL and Verilog across FPGA platforms. Timing closure, synthesis optimisation, AXI-Stream interfaces, hardware verification and validation. ASIC synthesis and PPA analysis via open-source flows including OpenLane.
Hardware architectures where timing predictability is a design constraint. Fixed-latency pipelines, cycle-accurate execution, and buffer-free designs for safety-critical and latency-sensitive applications.
High-throughput hardware architectures for data-intensive applications. Line-rate packet processing, hardware accelerators, and pipelined FPGA designs optimised for sustained throughput at scale.
Custom RISC-V ISA extensions for resource-constrained environments. Arithmetic acceleration techniques for FPGA fabrics under area and power constraints. Edge ML inference on legacy and low-cost FPGA fabrics.
EM side-channel characterisation of embedded and specialist hardware. Physical trace acquisition and ML-based classification. Research into capability-based security enforcement mechanisms at the hardware level.
Engineering experience across operational defence environments. Familiarity with the constraints, standards, and disciplines of defence-grade engineering.
Ongoing Research
EM side-channel characterisation of the CHERIoT-Ibex processor on the Sonata FPGA platform. Near-field trace acquisition via RTL-SDR, targeting capability check pass/fail leakage. ML-based classification over labelled trace sets. No prior published EM analysis of CHERI capability hardware exists in the literature.
Implementation of CHERI capability checking hardware on a custom RV32IM soft core. Cycle-accurate measurement of capability enforcement overhead — area, timing, and determinism — on a minimal FPGA platform. Assessing whether capability validation latency is sufficiently predictable for real-time embedded deployment.
Investigation of electromagnetic leakage from custom instructions implemented in reconfigurable logic. Examining whether distinct logic structures produce distinguishable EM signatures, and the security implications for FPGA deployments using custom ISA extensions. Builds on a verified RV32IM soft core platform with established bare-metal benchmarking infrastructure.
Publications
IEEE COOL Chips 29 — Tokyo, April 2026
Zero-Jitter Packet Parsing: A Deterministic Buffer-Free FPGA Architecture for Fixed-Latency Flow ExtractionA buffer-free hardware architecture for extracting L2–L4 flow telemetry at line rate. Fixed 11-cycle metadata extraction latency with zero observed variance under randomised traffic, implemented on Xilinx Zynq-7020.
Presented at the IEEE Symposium on Low-Power and High-Speed Chips and Systems, Tokyo.
Read paper →About
Founder & Principal Engineer
Padraic Sheehan is the founder of Galena, an independent hardware engineering and security research practice working with defence and technology organisations. His work focuses on FPGA design, deterministic real-time systems, and the security of embedded hardware.
Padraic served as a Lieutenant in the Irish Naval Service, where he was second-in-command of the Electrical and Electronic Section, a 25-strong technical team responsible for the electrical and electronic systems across a fleet of eight ships valued at approximately €300 million.
Earlier in his career, Padraic worked as an electronic engineer in the test engineering department at Boston Scientific in Clonmel, developing and validating test systems for implantable cardiac devices, including pacemakers and defibrillators.
Padraic presented work on deterministic FPGA packet processing at the IEEE Symposium on Low-Power and High-Speed Chips and Systems (COOL Chips) in Tokyo in 2026. He will begin an MPhil by research at the University of Cambridge in October 2026, specialising in hardware security.
He holds a BEng in Electronic and Computer Engineering and is a member of Engineers Ireland and the Army and Navy Club, London. Padraic speaks Irish and French, is an avid swimmer, and has a deep interest in philosophy and Irish literature.
Contact
padraic@galenalab.com